Powering Future Technology Nodes | PFTN semiconductor

On May 8, the International EDA Symposium ISEDA 2026 was grandly held in Singapore. PFTN (hereinafter referred to as PFTN) showcased its core products and solutions, engaging with world-renowned experts, scholars, and leading industry players to discuss technological breakthroughs for advanced process nodes. Throughout the conference, the PFTN booth attracted a continuous stream of international visitors, with vibrant exchanges and growing interest.

During a dedicated technical presentation, PFTN delivered a report titled "Modernizing TCAD: High-Performance Solvers and GPU-Accelerated Architectures for Sub-2nm Technology Development," demonstrating its latest advancements and forward-looking strategies in the development of manufacturing-oriented EDA toolchains.

The report provided an in-depth analysis of how, as semiconductor processes approach the 2nm node and beyond, the rapid introduction of new materials, complex process equipment, and 3D device structures has created a highly coupled multi-dimensional design space spanning materials, processes, devices, and design — imposing higher demands on simulation capabilities. To address the bottlenecks of traditional solvers in computational scale and physical modeling, PFTN proposed a new roadmap for modernizing TCAD.

PFTN introduced a TCAD framework tailored for advanced technology nodes. By incorporating GPU-accelerated computing architectures, the framework dramatically improves simulation efficiency. Furthermore, with new-generation solvers capable of handling multi-scale and multi-physics coupling problems, users can more accurately simulate critical physical phenomena in advanced semiconductor manufacturing processes. These technologies effectively support the development of more complex and finer-grained process and device requirements.

In addition, PFTN demonstrated how these advanced simulation tools can be integrated into a next-generation DTCO (Design-Technology Co-Optimization) collaborative system, bridging the gap from fundamental physics research to industrial process development. By building a scalable, high-performance AI-enabled simulation and prediction platform, PFTN lays a solid foundation for the R&D of next-generation semiconductor process technologies.

During the event, Professor Yee-Chia Yeo, Executive Vice President of A*STAR and renowned professor at the National University of Singapore (NUS) — an internationally acclaimed expert in the semiconductor field — visited PFTN Booth B2 and provided his endorsement of the company’s technology.

Professor Yee-Chia Yeo, a former member of TSMC and BT Laboratories, holds 88 U.S. patents and has published over 370 academic papers. He is a two-time recipient of the IEEE Paul Rappaport Award and a pioneer in strained-channel and high-mobility transistor technologies. Professor Yeo highly commended PFTN’s innovations in 2nm TCAD and DTCO.

We firmly believe that in the advanced process era, barriers between design and manufacturing must be broken through bidirectional collaboration. PFTN is committed to delivering truly deployable technical services, providing a one-stop DTCO “software + service” total solution to help customers achieve faster, more cost-effective, and superior chip manufacturing development in the 2nm era.

Starting from Singapore and reaching the global semiconductor supply chain, PFTN will continue to deepen its expertise in EDA foundational technologies, strengthen industry partnerships, and continuously enhance its core competitiveness and market influence — jointly shaping a new chapter of high-quality development in the 2nm era with industry partners.